1EUV Extreme ultraviolet lithography
Lithography is the step that prints a chip's pattern onto silicon. EUV does it, in ASML's words, “using light with a wavelength of just 13.5 nm,” and ASML calls the technology “entirely unique to ASML.”
A pen. You cannot draw a line thinner than the tip, and here the light is the tip. ASML's own rule: “The shorter the wavelength of light, the smaller the microchip features that can be printed.” Making this tip means hitting a falling drop of molten tin with two laser pulses, 50,000 times every second, in a vacuum, because EUV light is “absorbed by everything, even air.”
More than €6 billion over 17 years. That is what ASML says it put into EUV research. The industry started as a coalition in 1994, and then, ASML writes, “only ASML – with our partners and suppliers – continued work toward a viable system.” The 100th EUV system shipped at the start of 2020. In the third quarter of 2026 ASML sold 17 in three months. They were 49% of €8.37 billion of system sales, which works out to about €4.1 billion, or about €241 million a machine on ASML's rounded share.
Our ASML Q3 page, where the CEO said “we now expect that our supply as currently planned for both 2027 and 2028 will not fully meet the demand of our customers.” Non-current contract liabilities, the line that carries long-dated prepayments, went from €3.57 billion to €9.30 billion in one quarter.
EUV does not print the whole chip. ASML says it handles “the most intricate layers on a chip, with the rest of the layers printed using various DUV systems,” the older deep ultraviolet machines. In that same quarter ASML sold 40 immersion DUV systems against the 17 EUV. And ASML makes the machine. The chipmaker runs it.
2CoWoS TSMC's packaging that joins processors and memory
TSMC calls CoWoS its “advanced 2.5D packaging technology,” built by “integrating multiple SoCs and high-bandwidth memory stacks.” An SoC here is the processor. The letters stand for chip on wafer on substrate unverified, a reading from secondary summaries, because the TSMC pages we read use only the acronym.
A small building plot. The processors are houses, the memory stacks are towers next door, and the plot itself, a slab of silicon TSMC calls an interposer, carries the streets between them. Short streets are the point. Data does not have far to travel.
2012, and about 2,700 square millimeters. TSMC says CoWoS entered volume production in 2012, ten years before “the advent of generative AI in late 2022” made demand “even greater.” A process can spend a decade in a factory before demand catches up with it. The CoWoS-S interposer now reaches 3.3 times the reticle, the pattern plate from term one, or about 2,700 square millimeters. As a square, that is about 52 millimeters a side. Bigger builds move to the CoWoS-L or CoWoS-R versions.
Our July 13 weekly: “The HBM constraint has moved from wafer to package.” Our August 24 weekly had “CoWoS runs behind AI-chip demand,” with reported capacity of roughly 130 to 140 thousand wafers a month by late this year unverified. TSMC does not give that figure on the pages we read.
Packaging sounds like the cardboard box. TSMC's own line: “Packaging technologies were once considered simple backend processes, almost an inconvenience.” Then: “Times have changed.” CoWoS is also one company's trademark, not the name of the category. Rivals are building their own, and Intel said on its Q3 call that it expects to announce external customers for advanced packaging within two quarters.
3Hybrid bonding Joining chips copper to copper, with no solder bumps
Besi, which sells the machines, says hybrid bonding “replaces traditional reflowed flip chip solder bumps with a direct copper-to-copper connection between a chip and a wafer.”
A coat. Solder bumps are buttons: each one is a separate lump, and only so many fit. Hybrid bonding is a zipper: the two sides close directly into each other, with far more teeth in the same length. A zipper jams on a crumb, too. Besi's machine keeps its working area at ISO3 cleanliness.
200 nm to 100 nm to 50 nm. That is how closely Besi's machines can place a chip: 200 nm at launch in 2021, 100 nm in systems first shipped in 2024, and a 50 nm prototype in 2025. Its roadmap chart runs from fewer than 100 connections per square millimeter to more than 1,000,000, with hybrid bonding at the far end. Orders since 2021 total more than 150 systems from 18 customers. The tool is young, and its seller puts the 2030 market at €1,200 million in a mid case.
Not on a tkal page by name yet, which is part of why it is here. The nearest is our Applied Materials investor day recap, where advanced packaging is one of three areas expected to drive around 75 percent of equipment growth from 2025 to 2030. Besi's annual report records Applied buying a 9% stake in Besi.
It is not the only way to join chips, and the case for it comes mostly from the people selling it. Thermo compression bonding still uses solder bumps, with heat and pressure, and Besi sells that too, calling the two “compatible and complementary.” Besi says hybrid bonding “has the potential” to lead for chips below 3 nanometers. Potential is the honest word. TSMC's chip-stacking page describes a bond pitch that “starts from the sub-10µm rule” without using the words hybrid bonding at all, so we cannot tell you from that page how far the two terms overlap.
Should you care?
If you follow chip stocks: these three steps are where a shortage can sit even when demand is plain to see, which is why the supply statements matter as much as the orders. The thing to watch is whether ASML takes its 2028 capacity plan past the 30% increase it has already described, against its statement that planned supply will not fully meet demand in 2027 and 2028.
If you just use AI: the price and the speed of what you use depend partly on machines most people never hear about. Better software does not print a finer line.
This is education, not advice. Nothing here says to buy or sell anything.